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October 19 @ 8:00 am - October 20 @ 5:00 pm
19th – 20th October, 2023
Hosted by VLSI Research Group
School of Electrical and Electronics Engineering,
VIT Bhopal University
Dr. Vishal Sharma
PhD, SoC Design Engineer at Intel Technology
Dr. Ankur Beohar
Topic: Devices to Circuits, Dive into low Power Nanoscale Devices and Explore circuit applications & gate structures.
Dr. Deep Chandra Upadhyay
Topic: Nanostructures in Sensors, Learn about nanostructures and Discover their use in high-performance photodetectors.
Dr. Pallabi Sarkar
Topic: Optimization in ASIC Design, Deep dive into Digital System Design optimization and Focus on Architectural Level Synthesis for ASIC Design.
Ms. Sonal Gupta
Topic: VLSI Systems via Vivado and Get hands-on with an application-based approach.
Dr. Vishal Sharma
Hands-On Session: Analog VLSI Methodologies, Hands on experiece on Analog VLSI Design, Schematic design, simulation and analysis, and Efficient Layout design(with DRC & LVS check) using Cadence Virtuoso.
Registration fee Details
For all participants : 250/-
Last date of Registration: 10th October
Exclusively curated for B.Tech, M.Tech, M.E., PhD scholar and faculty from Electronics, Electrical, Instrumentation, & Computer Science. Participate in hands-on workshops, acquainting you with advanced VLSI tools.
Early Bird registration: Just Rs. 250/- per person.
Account Details (for NEFT payments)
Account Holder: VIT SEEE CLUB
Account No.: 7107689443
IFSC Code: IDIB000V143
Branch Code: 02953
Bank Name: INDIAN BANK
Registration Link (Please register after completion of payment)
Last date for registration: 10th October.
Confirmation to the participants: 11th October.
Participants will receive an e-certificate when they attend the session.
Dr. DEBASHIS ADHIKARI
Madhya Pradesh, India.