A low power arithmetic unit driven motion estimation and intra prediction accelerators with adaptive Golomb–Rice entropy encoder for H.264 encoders on FPGA

Due to the H.264 encoder’s exceptional performance in video compression, its use has been growing in the recent past. However, reducing the power consumption of video compression remains a difficult problem for H.264 codecs. Therefore, the goal of the proposed study is to optimize the fundamental parts of H.264 in order to improve performance and reduce the amount of power that H.264 encoders on FPGA consume. The elements such as Motion Estimation, Intra-prediction, Transform Unit, and Entropy Encoder are optimized for this goal by means of the efficient approaches presented in the suggested work. First, Block Matching Algorithms’ basic building blocks can be optimized to switch out the Motion Estimation unit. The suggested study introduces low-power arithmetic units, such as an add-one circuit-based Carry Sequential Adder and Sum, to build the Block Matching Algorithms.

Dr. H. AZATH
Program Chair,
Integrated M.Tech Cyber Security.